em microelectronic-marin sa H6061 1 3 v self recovering watchdog features n watchdog fully operational from 2.7 to 5.25 v n regulated dc voltage monitor, internal voltage reference n self recovering watchdog function: reset goes active after the 1st timeout period, reset goes inactive aga in after the 2nd timeout period, repeated active reset signal until the system recovers n standard timeout period and power-on reset time (100 ms), externally programmable from 3 ms to 3 mins if required n works down to 1.6 v supply voltage n low voltage alarm prior to reset on power-down n reset outputs of both polarities n open drain outputs n small footprint so8 and dip8 packages description the H6061 is a combined initialiser, watchdog and voltage monitor. the circuit is a low voltage low power monolithic cmos device combining a series of voltage comparators and a programmable timer on the same chip. the device is specially suited to telecommunications applications where 3 v working is expected, for functions such as supply voltage and microprocessor monitoring. the reset outputs are self recovering after a watchdog timeout, enabling the circuit to work with standalone systems without any external push-switch or control signal to restart after a watchdog timeout. the circuit provides a reset signal of both polarities. the state of the outputs is defined down to 1.6 v. an internal debouncer ensures power-up perfomance for fast-rise supply lines. applications n microprocessor and microcontroller systems n point of sales equipment n telecom products n automotive subsystems n microcontroller 68hc05 applications typical operating configuration pin assignment dip8 / so8 v in v ss rc tcl v dd res save res fig. 2 H6061 fig. 1 v in H6061 tcl save res v dd res v ss 5 v gnd nmi res i/o m p
H6061 2 absolute maximum ratings parameter symbol conditions voltage v dd to v ss voltage at any pin to v ss voltage at any pin to v dd voltage at v in to v ss current at any output storage temperature electrostatic discharge max. to mil-std-833c method 3015 v dd v min v max v in max i max t sto v smax - 0.3 to + 5.6 v - 0.3 + 0.3 + 12 v 10 ma - 65 to + 150 c 1000 v table 1 stresses above these listed maximum ratings may cause permanent damage to the device. exposure beyond specified operating conditions may affect device reliability or cause malfunction. handling procedures this device has built-in protection against high static voltages or electric fields; however, it is advised that normal precautions be taken as for any other cmos component. unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the supply voltage range. unu s ed inputs must always be tied to a defined logic voltage level. operating conditions parameter symbol min. typ. max. units operating temperature industrial supply voltage monitored input vo ltage rc-oscillator program m - ing (see fig. 15) external capacitance * external resistance t a v dd v in c1 r1 -40 2.7 0 10 +85 5.25 12 1 c v v m f k w * leakage < 1 m a table 2 electrical characteristics v dd = 5.0 v, t a = - 40 to +85 c , unless otherwise specified parameter symbol test conditions min. typ. max. units v dd activation threshold v dd deactivation threshold supply current input v in , tcl leakage current tcl input low level tcl input high level leakage on pins , , res o/p drive logic low v on v off i dd i p v il v ih i olk i ol i ol i ol t a = 25 c t a = 25 c rc open, tcl at v dd or v ss v ss < v ip H6061 3 timing characteristics v dd = 5.0 v, t a = - 40 to + 85 c ( - 40 to + 125 c for extended temperature range version), unless otherwise specified parameter symbol test conditions min. typ. max. units propagation delays to output pins v in to output pins logic transition times on all output pins timeout period t tcl input pulse width power-on reset debounce fastest pulse v in with debounce t dido t aido t tr t to t tcl t db t vinl excluding debounce time t db load 10 k w , 100 pf rc open, unshielded, t a = 25 c - 40 to +85 c 60 150 10 250 4 30 100 t to /64 500 10 100 1 6 0 ns m s ns ms ns ms m s table 5 timing waveforms voltage reaction: v dd monitoring voltage reaction: v i n monitoring tcl v dd v on v off v in monitoring enabled fig. 3 v in v sh v sl v rl 0 save res res t to t db t to t db t vinl conditions: v dd > v on . no timeout sequence. fig. 4 timer start power-on reset timer stop timer start power-on reset no power-on reset (as v in > v rl )
H6061 4 timer reaction combined voltage and timer reaction block diagram v in v sh v sl v rl save res res tcl initialisation res res timeout recover timer reset timer stop t to t to t to t db fig. 6 res res tcl timeout timer reset timer reset timer reset t to t to fig. 5 t tcl t to t to conditions: v in > v rl after power-up sequence band-gap reference save control reset control osc timer tcl save res res v in v sh v sl v rl v ss rc + + + + fig. 7
H6061 5 pin description pin name function 1 v in voltage monitoring input 2 timer clear input signal 3 rc rc oscillator tuning input 4 v ss gnd terminal 5 r eset output , open drain 6 save output , open drain 7 res positive reset output , open drain 8 v dd positive supply voltage table 6 functional description thresholds and outputs the H6061 has open-drain outputs and voltage thresholds on pin v in of typically 1.5 v. internal voltage comparators the voltage comparators detect the voltage applied to pin v in and compare it with thresholds v sh , v sl and v rl . the H6061 is designed for monitoring regulated dc voltages and has bandgap thresholds independent of v dd . the reaction of the H6061 to voltage changes on pin v in is given in fig. 4. during powering-up, the outputs are active. after v in reaches the v sh level, pin save deactivates after a short debounce time t db to allow for fast ramp-ups. the initialization time t to then passes before the two reset outputs go inactive. thereafter, when the voltage on pin v in falls below the v sl level, pin save goes active low as a first warning. if v in then drops below the v rl level, the reset signals go active and are guaranteed down to 1.6 v. the reset outputs react also to timeouts (see ?timer clearing?). note that when the supply voltage v dd is below the level v off (about 2.2 v), all outputs are in the active state for any allowed voltage of v in . voltage programming the H6061 was designed to give the best compromise in normal usage (see table 3). its voltage threshold can be programmed by an external resistor divider or a potentiometer to react at proportionally higher voltage levels (see fig. 8 below). voltage programming timer programming a single timeout period t to is used for the initialization reset duration and the watchdog timeout. with pin rc unconnected, the on-chip rc oscillator and divider chain give a timeout period t to of typically 100 ms. a resistor to v dd will shorten this time, and a capacitor to v ss will lengthen it (see fig. 11). an approximation for calculating trial values given in milliseconds by the formula: r 1 min. = 10 k w , c 1 max. = 1 m f if r 1 is in m w and c 1 in pf, t to will be in ms. choice of component values must be determined in practice. to have a square wave of period 2t to , simply connect pin tcl to v dd or v ss and take the signal output from a reset pin. timer clearing a negative edge or pulse at the tcl input longer than 150 ns will clear the timer and deactivate the reset outputs under normal running conditions (see fig. 3). tcl will however have no effect either when v dd < v off or during the initialization period before the deactivation of the reset pins. combined voltage and timer action in fig. 6 is a typical sequence of power-up, watchdog run, and power-down. during initialization the save pin deactivates one debounce delay time t db after v in rises above v sh , or when the power line v dd rises above v on , whichever happens last. the reset pins only deactivate one timeout period t to afterwards to free the watchdog timer and end the initialization. note that either v in falling below v rl threshold or v dd below v on will cause an initialization upon recovery. following initialization, the watchdog timer will time out after time t to unless at least one tcl pulse clears it. on timeout the reset pins reactivate for a further t to period before deactivating again for another try. a tcl pulse will deactivate any timeout reset, and another tcl pulse must follow within a time t to to keep reset inactive. if no tcl pulses come at all, the reset pins go square-wave. power-down overrides all this however. a falling voltage on v in gives a warning save = 0 signal at v in = v sl before activating the reset pins as soon as v in drops below v rl . the H6061 has fixed thresholds and low hysteresis for monitoring regulated dc lines. additional protection is provided in case v dd supply falls over about 10% below v on which thereupon activates all outputs at once. tcl res save H6061 v dd +3 v / +5 v v in v ss fig. 8 192 . 8 6 . 1 ) + + + = r 0.8 - v 4.8 c (32 0.75 1 dd 1 to t
H6061 6 typical applications microprocessor watchdog with voltage monitor selection of watchdogs for each application the H6061 is designed for monitoring regulated dc voltages anywhere between 2.7 and 5.25 v. typically, it is used to monitor v dd with pin v in tied to the midpoint of a voltage divider (see fig. 8). this arrangement has the advantage of being able to trigger at selectable voltage limits, i. e. it can be used where the regulated voltage is below 5 vdc. industrial heavy-duty utilisation the H6061 debounce protects against reactions due to fast-rise power lines, but absolute maximum ratings must be respected. with its flexibility of voltage programming and supply voltage the H6061 can allow for voltage drops along supply lines, so it can be placed remotely, like on plug-in boards (see fig. 9). the H6061 is suitable for supply voltages down to 2.7 vdc. as the H6061 is designed to be sensitive to voltage changes, fast switching lines, like address/data bus lines should not be run between the v dd and v ss supply lines near the H6061 without ground-plane shielding. tracks from components to pin rc must be kept very short. pin rc if left free should be shielded with a ground ring in noisy environments. the H6061 has only 40 mv hysteresis specially for monitoring regulated dc. pin v in must be protected from any significant mains ripple or rfi (see fig. 10). it should be placed as near as possible to the point where voltage is to be monitored. pin v in is protected by an internal resistor (nominal 15 k w ) against voltages in excess of v dd . in some environments this may however pick up enough mains ripple or rfi to distort the voltage detection thresholds or even cause unwanted sporadic resets in the absence of adequate shielding or filtering on v in . the H6061 has sufficient immunity to ripple and interference on the v dd supply line, but if it is important that a system meet severe criteria for injected spikes and rfi, then care must be taken also decouple v dd from these influences, as system protection must continue even under these conditions. with normal series voltage regulators, the regulated 5 vdc output voltage follows the dc rough voltage within 1.5 v on powering up. if the application has pin v in monitoring the dc rough, the internal inputs to the on-chip comparators will not rise above v dd if the H6061 is correctly programmed. with switched-mode power supplies however, the dc-rough voltage on power-up rises almost to its working level before the 5 vdc line starts to ramp up. the H6061 has been specially designed to work under these extreme conditions but care must be taken not to exceed absolute maximum ratings. in addition to the voltage monitoring on pin v in , a final protection is given by the H6061 monitoring its own v dd supply. if a system malfunction causes v dd to fall below v off even though pin v in stays high, then all outputs go active at once. address decoder microprocessor ram cs disable H6061 v dd save res v in tcl rc 5 v monitored voltage r 1 =470 k w c 1 = 220 pf res nmi t to = ~250 ms fig. 9 rd latched address bus sel v ss
H6061 7 combined supply monitor, initializer and watchdog external programming of rc oscillator r1 note: if external components r1 and c1 are used, a tighter timeout period tolerance can be achieved. c1 increases t to r1 shortens t to this circuit provides independent programming of both timeout period and power-on reset delay. fig. 11 c1 r1 c1 H6061 H6061 H6061 tcl rc v ss v dd to res res to v dd tcl rc v ss tcl rc v ss v dd to res H6061 nominal thresholds: v sh 2.84 v sl 2.77 v rl 2.70 33 k w 39 k w v in v ss 1) tcl v dd save res fig. 10 3 vdc v in shield 1) or decoupling 2) optional against interference 2)
H6061 8 ordering information industrial temperature range ( - 40 to +85 c) type 1) package H6061 25 8p dip8 H6061 25 8s so8 extended temperature r ange ( - 40 to +125 c) type package H6061 25x 8p dip8* H6061 25x 8s so8* * non-stock items chip form on request ? 2000 em microelectronic-marin sa, 10/00, rev. f/327 em microelectronic-marin sa cannot assume any responsibility for use of any circuitry described other than entirely embodied in an em microelectronic-marin sa product. em microelectronic-marin sa reserves the right to change the circuitry and specifications without notice at any time. you are strongly urged to ensure that the information given has not been superseded by a more up-to-date version. em microelectronic-marin sa, ch - 2074 marin, switzerland, tel. (+41) 32 - 755 51 11, fax (+41) 32 - 755 54 03
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